1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including an analog signal processing circuit having MOS transistors.
2. Description of the Related Art
In a semiconductor integrated circuit, in particular, in an analog signal processing circuit, which includes MOS transistors, difference in characteristics between adjacent MOS transistors is required to be small enough. The analog signal processing circuit includes an operational amplifier and a current mirror circuit, and has a function of producing a plurality of current sources with a certain ratio to compare and amplify a plurality of voltages with high precision. Having the same structure and layout the MOS transistors, which are used for the analog signal processing circuit, are assumed to have the same threshold voltage, mutual conductance, and sub-threshold characteristics including a leak current, as a precondition to circuit operation. Differences among the characteristics generate an offset voltage in the operational amplifier and a current error in the current mirror circuit, giving possible degradation to the product characteristics itself.
Accordingly, in order to produce the plurality of MOS transistors which are required to have the same characteristics, various measures are taken, including not only a method of equalizing fundamental device parameters, such as adjusting a channel length, a channel width, a contact shape, and a distance between a contact and a channel to the same values, but also typical other methods such as a method of aligning channel directions, a method of minimizing a distance between MOS transistors, and a method of producing a circuit having a plurality of MOS transistors which are cross-coupled. In order to suppress a deviation in threshold voltage, the channel length and the channel width are generally extended to minimize a variation in characteristics due to a deviation in size caused during a manufacturing process.
These measures accompany increase of the device size and of the circuit area, opposing reduction in cost and size. In particular, when the scale of the analog signal processing circuit becomes larger, the trade-off becomes significant, and hence it is difficult to obtain benefits from a miniaturization technology used for a digital signal processing circuit. In addition, in a case of a digital and analog mixed IC, a process combination between them may also be limited in some cases.
Parameters such as gate oxide film thickness and channel impurity concentration are main candidates for affecting the variation in characteristics and deviation of a MOS transistor. However, technologies accompanying the device miniaturization, on the other hand, have an aspect of suppressing the variation in characteristics of the MOS transistor. For example, the gate oxide film thickness giving a dominant effect to the characteristics of the MOS transistor is less likely to become a factor for characteristics variation along with the improvement in film thickness control.
The improvement of patterning control during a photolithography process and an etching process directly leads to a reduction in size deviation, suppressing the variation in characteristics due to a shape effect caused by reduction of the device size, and hence becomes a technology for accelerating the reductions in size and cost.
With the above mentioned progress of the technologies in the background, the variation in channel concentration, in particular, the variation in concentration of a well region formed in a semiconductor substrate is an increasing factor of the variation of characteristics of a MOS transistor.
FIG. 2 illustrates a conventional semiconductor integrated circuit device. A normal two-dimensional arrangement of MOS transistors is described with reference to FIG. 2. P-type and N-type well regions are formed in a P-type semiconductor substrate. P-channel MOS transistors 101 are normally formed within an N-type well region 6. Therefore, a plurality of P-channel MOS transistors 101 are grouped for a single circuit block and arranged adjacent to each other within the single N-type well region 6 of the semiconductor substrate. Similarly, N-channel MOS transistors 102 are arranged for a single circuit block adjacent to each other within the predetermined P-type well region 5.
In this case, the P-channel MOS transistors 101 are particularly arranged within the N-type well region 6 having a finite space, and hence a device may be arranged close to a boundary between the N-type well region 6 and the P-type well region 5.
An analog circuit block is desired to have a uniform characteristic without a variation in respective transistor characteristics. Therefore, it is necessary to obtain a uniform impurity concentration within the same N-type well region.
Methods of reducing the variation in transistor characteristics in the analog circuit are disclosed in, for example, JP 06-268453 A, JP 09-266257 A, and JP 2003-243529 A.
However, the conventional well region formation method using the semiconductor process as described above has the following problem. The thermal treatment for forming the oxide film is performed after the impurity implantation for forming the N-type well region. During the thermal treatment, a concentration of a boundary portion of the N-type well region is changed by diffusion. To be specific, the impurity is diffused in the lateral direction, and hence the concentration of the boundary region reduces. The thermal treatment is further performed as compared to the case of forming the P-type well region. Therefore, the degree of reduction in concentration of the vicinity of the boundary portion of the N-type well region is larger than the degree of reduction in concentration of the vicinity of the boundary portion of the P-type well region.
Thus, the MOS transistors arranged close to the boundary regions, in particular, the P-channel MOS transistor 101 located on the N-type well region side 6 as shown in FIG. 2 is more likely to cause the variation in characteristic due to the change in concentration.